Semiconductor device structure

ABSTRACT

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a multilayer stack over the base. The semiconductor device structure includes a gate stack over the substrate and wrapping around the multilayer stack. The semiconductor device structure includes a dielectric layer over the base and covering a first sidewall of the multilayer stack. A first upper surface of the dielectric layer is lower than a second upper surface of the multilayer stack. The semiconductor device structure includes a stressor over a second sidewall of the multilayer stack. The first sidewall is opposite to the second sidewall.

CROSS REFERENCE

This application is a Divisional of U.S. application Ser. No.16/571,751, filed on Sep. 16, 2019, the entirety of which isincorporated by reference herein.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. Technological advances in IC materials and design have producedgenerations of ICs. Each generation has smaller and more complexcircuits than the previous generation. However, these advances haveincreased the complexity of processing and manufacturing ICs.

In the course of IC evolution, functional density (i.e., the number ofinterconnected devices per chip area) has generally increased whilegeometric size (i.e., the smallest component (or line) that can becreated using a fabrication process) has decreased. This scaling-downprocess generally provides benefits by increasing production efficiencyand lowering associated costs.

However, since feature sizes continue to decrease, fabrication processescontinue to become more difficult to perform. Therefore, it is achallenge to form reliable semiconductor devices at smaller and smallersizes.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It shouldbe noted that, in accordance with standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A-1M are perspective views of various stages of a process forforming a semiconductor device structure, in accordance with someembodiments.

FIG. 1E-1 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line I-I′ in FIG. 1E, in accordancewith some embodiments.

FIG. 1F-1 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line I-I′ in FIG. 1F, in accordancewith some embodiments.

FIG. 1G-1 is a top view of the semiconductor device structure of FIG.1G, in accordance with some embodiments.

FIG. 1G-2 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line I-I′ in FIG. 1G-1, in accordancewith some embodiments.

FIG. 1G-3 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line II-II′ in FIG. 1G-1, inaccordance with some embodiments.

FIG. 1H-1 is a top view of the semiconductor device structure of FIG.1H, in accordance with some embodiments.

FIG. 1H-2 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line I-I′ in FIG. 1H-1, in accordancewith some embodiments.

FIG. 1H-3 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line II-II′ in FIG. 1H-1, inaccordance with some embodiments.

FIG. 1J-1 is a perspective view of a portion of the semiconductor devicestructure of FIG. 1J, in accordance with some embodiments.

FIG. 1K-1 is a perspective view of a portion of the semiconductor devicestructure of FIG. 1K, in accordance with some embodiments.

FIG. 1L-1 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line I-I′ in FIG. 1L, in accordancewith some embodiments.

FIG. 1M-1 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line I-I′ in FIG. 1M, in accordancewith some embodiments.

FIG. 1M-2 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line II-II′ in FIG. 1M, in accordancewith some embodiments.

FIG. 2 is a cross-sectional view of a stage of a process for forming asemiconductor device structure, in accordance with some embodiments.

FIG. 3 is a cross-sectional view of a semiconductor device structure, inaccordance with some embodiments.

FIG. 4 is a cross-sectional view of a semiconductor device structure, inaccordance with some embodiments.

FIG. 5 is a cross-sectional view of a semiconductor device structure, inaccordance with some embodiments.

FIGS. 6A-6B are cross-sectional views of various stages of a process forforming the semiconductor device structure of FIG. 5, in accordance withsome embodiments.

FIGS. 7A-7E are cross-sectional views of various stages of a process forforming a semiconductor device structure, in accordance with someembodiments.

FIG. 7C-1 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line I-I′ in FIG. 7C, in accordancewith some embodiments.

FIG. 7D-1 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line I-I′ in FIG. 7D, in accordancewith some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the subject matterprovided. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as “beneath,” “below,”“lower,” “above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly. It should be understoodthat additional operations can be provided before, during, and after themethod, and some of the operations described can be replaced oreliminated for other embodiments of the method.

Some embodiments of the disclosure are described. Additional operationscan be provided before, during, and/or after the stages described inthese embodiments. Some of the stages that are described can be replacedor eliminated for different embodiments. Additional features can beadded to the semiconductor device structure. Some of the featuresdescribed below can be replaced or eliminated for different embodiments.Although some embodiments are discussed with operations performed in aparticular order, these operations may be performed in another logicalorder.

Embodiments of the disclosure form a semiconductor device structure withFinFETs. The fins may be patterned by any suitable method. For example,the fins may be patterned using one or more photolithography processes,including double-patterning or multi-patterning processes. Generally,double-patterning or multi-patterning processes combine photolithographyand self-aligned processes, allowing patterns to be created that have,for example, pitches smaller than what is otherwise obtainable using asingle, direct photolithography process. For example, in one embodiment,a sacrificial layer is formed over a substrate and patterned using aphotolithography process. Spacers are formed alongside the patternedsacrificial layer using a self-aligned process. The sacrificial layer isthen removed, and the remaining spacers may then be used to pattern thefins.

The gate all around (GAA) transistor structures may be patterned by anysuitable method. For example, the structures may be patterned using oneor more photolithography processes, including double-patterning ormulti-patterning processes. Generally, double-patterning ormulti-patterning processes combine photolithography and self-alignedprocesses, allowing patterns to be created that have, for example,pitches smaller than what is otherwise obtainable using a single, directphotolithography process. For example, in one embodiment, a sacrificiallayer is formed over a substrate and patterned using a photolithographyprocess. Spacers are formed alongside the patterned sacrificial layerusing a self-aligned process. The sacrificial layer is then removed, andthe remaining spacers may then be used to pattern the GAA structure.

FIGS. 1A-1M are perspective views of various stages of a process forforming a semiconductor device structure, in accordance with someembodiments. As shown in FIG. 1A, a substrate 110 is provided, inaccordance with some embodiments. The substrate 110 includes a lowerportion 112 and a multilayer structure 114, in accordance with someembodiments. The multilayer structure 114 is formed over the lowerportion 112, in accordance with some embodiments.

The lower portion 112 includes, for example, a semiconductor substrate.The semiconductor substrate includes, for example, a semiconductor wafer(such as a silicon wafer) or a portion of a semiconductor wafer. In someembodiments, the lower portion 112 is made of an elementarysemiconductor material including silicon or germanium in a singlecrystal, polycrystal, or amorphous structure.

In some other embodiments, the lower portion 112 is made of a compoundsemiconductor, such as silicon carbide, gallium arsenide, galliumphosphide, indium phosphide, indium arsenide, an alloy semiconductor,such as SiGe, or GaAsP, or a combination thereof. The lower portion 112may also include multi-layer semiconductors, semiconductor on insulator(SOI) (such as silicon on insulator or germanium on insulator), or acombination thereof.

In some embodiments, the lower portion 112 is a device wafer thatincludes various device elements. In some embodiments, the variousdevice elements are formed in and/or over the lower portion 112. Thedevice elements are not shown in figures for the purpose of simplicityand clarity. Examples of the various device elements include activedevices, passive devices, other suitable elements, or a combinationthereof. The active devices may include transistors or diodes (notshown). The passive devices include resistors, capacitors, or othersuitable passive devices.

For example, the transistors may be metal oxide semiconductor fieldeffect transistors (MOSFET), complementary metal oxide semiconductor(CMOS) transistors, bipolar junction transistors (BJT), high-voltagetransistors, high-frequency transistors, p-channel and/or n-channelfield effect transistors (PFETs/NFETs), etc. Various processes, such asfront-end-of-line (FEOL) semiconductor fabrication processes, areperformed to form the various device elements. The FEOL semiconductorfabrication processes may include deposition, etching, implantation,photolithography, annealing, planarization, one or more other applicableprocesses, or a combination thereof.

In some embodiments, isolation features (not shown) are formed in thelower portion 112. The isolation features are used to define activeregions and electrically isolate various device elements formed inand/or over the lower portion 112 in the active regions. In someembodiments, the isolation features include shallow trench isolation(STI) features, local oxidation of silicon (LOCOS) features, othersuitable isolation features, or a combination thereof.

The multilayer structure 114 includes sacrificial layers 114 a andchannel layers 114 b, in accordance with some embodiments. Thesacrificial layers 114 a and the channel layers 114 b are alternatelyarranged as illustrated in FIG. 1A, in accordance with some embodiments.It should be noted that, for the sake of simplicity, FIG. 1A shows fourlayers of the sacrificial layers 114 a and four layers of the channellayers 114 b for illustration, but does not limit the invention thereto.In some embodiments, the number of the sacrificial layers 114 a or thechannel layers 114 b is between 2 and 10.

The sacrificial layers 114 a are made of a first material, such as afirst semiconductor material, in accordance with some embodiments. Thechannel layers 114 b are made of a second material, such as a secondsemiconductor material, in accordance with some embodiments.

The first material is different from the second material, in accordancewith some embodiments. The first material has an etch selectivity withrespect to the second material, in accordance with some embodiments. Insome embodiments, the sacrificial layers 114 a are made of SiGe, and thechannel layers 114 b are made of Si.

In some other embodiments, the sacrificial layers 114 a or the channellayers 114 b are made of other materials such as germanium, a compoundsemiconductor such as silicon carbide, gallium arsenide, galliumphosphide, indium phosphide, indium arsenide, and/or indium antimonide,an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP,and/or GaInAsP, or combinations thereof.

The channel layers 114 b and the lower portion 112 are made of the samematerial such as Si, and the sacrificial layers 114 a and the lowerportion 112 are made of different materials, in accordance with someembodiments. In some other embodiments, the sacrificial layers 114 a,the channel layers 114 b, and the lower portion 112 are made ofdifferent materials, in accordance with some embodiments.

The sacrificial layers 114 a and the channel layers 114 b are formedusing a molecular beam epitaxy (MBE) process, a metal-organic chemicalvapor deposition (MOCVD) process, and/or another suitable epitaxialgrowth process.

As shown in FIG. 1A, a mask layer 120 is formed over the multilayerstructure 114, in accordance with some embodiments. The mask layer 120has trenches 122, in accordance with some embodiments. The trenches 122expose portions of the substrate 110 (or the multilayer structure 114),in accordance with some embodiments.

The mask layer 120 is made of an oxide material such as silicon dioxide(SiO₂), a nitride material such as silicon nitride (Si₃N₄), or anothersuitable material, which is different from the materials of thesubstrate 110 (or the multilayer structure 114), in accordance with someembodiments. The mask layer 120 is formed using a deposition process(e.g., a physical vapor deposition process or a chemical vapordeposition process), a photolithography process, and an etching process(e.g., a dry etching process), in accordance with some embodiments.

As shown in FIGS. 1A and 1B, the portions of the substrate 110 exposedby the trenches 122 are removed through the trenches 122, in accordancewith some embodiments. The removal process forms trenches 111 in thesubstrate 110, in accordance with some embodiments.

After the removal process, the remaining portion of the substrate 110includes a base 113 and fin structures 116, in accordance with someembodiments. The fin structures 116 are over the base 113, in accordancewith some embodiments. The base 113 is formed from the lower portion 112(as shown in FIG. 1A), in accordance with some embodiments.

Each fin structure 116 includes a bottom portion 115 and a portion ofthe multilayer structure 114, which includes the sacrificial layers 114a and the channel layers 114 b, in accordance with some embodiments.That is, each fin structure 116 includes portions of the sacrificiallayers 114 a and the channel layers 114 b, in accordance with someembodiments. The bottom portion 115 is formed from the lower portion 112(as shown in FIG. 1A), in accordance with some embodiments. The finstructures 116 are separated from each other by the trenches 111, inaccordance with some embodiments.

Thereafter, as shown in FIGS. 1A and 1B, the mask layer 120 is removed,in accordance with some embodiments. As shown in FIG. 1B, a dielectriclayer 130 and dielectric fins 140 are formed in the trenches 111, inaccordance with some embodiments. The dielectric layer 130 conformallycovers inner walls 111 a and bottom surfaces 111 b of the trenches 111,in accordance with some embodiments.

The dielectric layer 130 has trenches 132 respectively in the trenches111, in accordance with some embodiments. The dielectric fins 140 arerespectively formed in the trenches 132, in accordance with someembodiments. Each dielectric fin 140 extends out of the correspondingtrench 132, in accordance with some embodiments.

The dielectric layer 130 is made of oxide (such as silicon oxide),fluorosilicate glass (FSG), a low-k dielectric material, and/or anothersuitable dielectric material. The dielectric fins 140 are made of oxide(e.g., silicon oxide), nitride (e.g., silicon nitride, silicon carbonnitride, silicon oxycarbon nitride, titanium nitride, or tantalumnitride), carbide (e.g., silicon oxycarbide), metal oxide (e.g., oxidesof Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb,Dy, Ho, Hf, Er, Tm, Yb, Lu, and/or mixtures thereof), or anothersuitable insulating material, in accordance with some embodiments.

In some embodiments, the dielectric layer 130 and the dielectric fins140 are made of different materials with different etching rates underan etchant. The removal of the mask layer 120 and the formation of thedielectric layer 130 and the dielectric fins 140 includes: conformallydepositing a dielectric material layer (not shown) over the substrate110, wherein the dielectric material layer in the trenches 111 hastrenches 132; depositing a dielectric fin material layer over thedielectric material layer to fill the trenches 132; performing aplanarization process to remove the dielectric material layer and thedielectric fin material layer outside of the trenches 111 and the masklayer 120; and performing a selective etching process to remove an upperportion of the dielectric material layer, wherein the remainingdielectric material layer forms the dielectric layer 130, and theremaining dielectric fin material layer forms the dielectric fins 140.

The dielectric material layer (or the dielectric layer 130) may bedeposited by an atomic layer deposition (ALD) process, a chemical vapordeposition (CVD) process, or another applicable process. The dielectricfin material layer (or the dielectric fins 140) may be deposited by achemical vapor deposition process, an atomic layer deposition process, aphysical vapor deposition (PVD) process, or another applicable process.

As shown in FIG. 1C, gate stacks 150 and mask layers M1 and M2 areformed over the fin structures 116, the dielectric layer 130, and thedielectric fins 140, in accordance with some embodiments. Each gatestack 150 includes a gate dielectric layer 152 and a gate electrode 154,in accordance with some embodiments. The gate dielectric layer 152, thegate electrode 154, and the mask layers M1 and M2 are sequentiallystacked over the fin structures 116, in accordance with someembodiments.

The gate dielectric layer 152 conformally covers the fin structures 116,the dielectric layer 130, and the dielectric fins 140, in accordancewith some embodiments. The gate dielectric layer 152 is made of aninsulating material, such as oxide (e.g., silicon oxide), in accordancewith some embodiments. The gate electrode 154 is made of a semiconductormaterial (e.g. polysilicon) or a conductive material (e.g., metal oralloy), in accordance with some embodiments.

The formation of the gate dielectric layer 152 and the gate electrode154 includes: depositing a gate dielectric material layer (not shown)over the fin structures 116, the dielectric layer 130, and thedielectric fins 140; depositing a gate electrode material layer (notshown) over the gate dielectric material layer; sequentially forming themask layers M1 and M2 over the gate electrode material layer, whereinthe mask layers M1 and M2 expose portions of the gate electrode materiallayer; and removing the exposed portions of the gate electrode materiallayer and the gate dielectric material layer thereunder, in accordancewith some embodiments.

In some embodiments, the mask layer M1 serves a buffer layer or anadhesion layer that is formed between the underlying gate electrode 154and the overlying mask layer M2. The mask layer M1 may also be used asan etch stop layer when the mask layer M2 is removed or etched.

In some embodiments, the mask layer M1 is made of an oxide-containinginsulating material (e.g., silicon oxide), a nitride-containinginsulating material (e.g., silicon nitride, silicon carbide, siliconoxynitride, silicon oxycarbonitride, or silicon carbonitride), or ametal oxide material (e.g., aluminum oxide).

In some embodiments, the mask layer M1 is formed by a depositionprocess, such as a chemical vapor deposition (CVD) process, alow-pressure chemical vapor deposition (LPCVD) process, a plasmaenhanced chemical vapor deposition (PECVD) process, a high-densityplasma chemical vapor deposition (HDPCVD) process, a spin-on process, oranother applicable process.

In some embodiments, the mask layer M2 is made of an oxide-containinginsulating material (e.g., silicon oxide), a nitride-containinginsulating material (e.g., silicon nitride, silicon oxynitride, siliconoxycarbonitride, or silicon carbonitride), silicon carbide, or a metaloxide material (e.g., aluminum oxide). The mask layers M1 and M2 aremade of different materials, in accordance with some embodiments.

In some embodiments, the mask layer M2 is formed by a depositionprocess, such as a chemical vapor deposition (CVD) process, alow-pressure chemical vapor deposition (LPCVD) process, a plasmaenhanced chemical vapor deposition (PECVD) process, a high-densityplasma chemical vapor deposition (HDPCVD) process, a spin-on process, oranother applicable process.

After the formation of the mask layer M1 and the mask layer M2, the masklayer M1 and the overlying mask layer M2 are patterned by aphotolithography process and an etching process, so as to expose theportions of the gate electrode material layer.

As shown in FIG. 1D, a spacer layer 160 is formed over the finstructures 116, the dielectric layer 130, the dielectric fins 140, thegate stacks 150, and the mask layers M1 and M2, in accordance with someembodiments. In some embodiments, as shown in FIG. 1D, the spacer layer160 is a multi-layered structure.

The spacer layer 160 includes layers 162 and 164, in accordance withsome embodiments. The layer 164 is over the layer 162, in accordancewith some embodiments. The layers 162 and 164 are made of differentmaterials, in accordance with some embodiments. In some otherembodiments (not shown), the spacer layer 160 is a single-layeredstructure.

In some embodiments, the layer 162 or 164 is made of an oxide-containinginsulating material, such as silicon oxide. In some other embodiments,the layer 162 or 164 is made of a nitride-containing insulatingmaterial, such as silicon nitride (SiN), silicon oxynitride (SiON),silicon oxycarbonitride (SiOCN), or silicon carbonitride (SiCN). Thelayers 162 and 164 are formed using a deposition process, such as achemical vapor deposition (CVD) process, an atomic layer deposition(ALD) process, or a physical vapor deposition (PVD) process, inaccordance with some embodiments.

As shown in FIG. 1E, portions of the spacer layer 160 and upper portionsof the fin structures 116, which are not covered by the gate stacks 150and the spacer layer 160 over sidewalls of the gate stacks 150, areremoved, in accordance with some embodiments. After the removal process,the spacer layer 160 remains over opposite sidewalls of the gate stacks150, opposite sidewalls of the mask layers M1 and M2, and the topsurfaces 132 of the dielectric layer 130, in accordance with someembodiments.

The spacer layer 160 remaining over the opposite sidewalls of the gatestacks 150 and the opposite sidewalls of the mask layers M1 and M2 formsspacers 165, 166, 167, and 168, in accordance with some embodiments. Thespacer layer 160 remaining over the top surfaces 132 of the dielectriclayer 130 forms spacers 169, in accordance with some embodiments.

The removal process forms recesses 116 a in the fin structures 116, inaccordance with some embodiments. Each multilayer structure 114 isdivided into multilayer stacks 114S by the recesses 116 a, in accordancewith some embodiments. Each multilayer stack 114S includes four layersof the sacrificial layers 114 a and four layers of the channel layers114 b, in accordance with some embodiments.

FIG. 1E-1 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line I-I′ in FIG. 1E, in accordancewith some embodiments. As shown in FIGS. 1E and 1E-1, each gate stack150 wraps around three of the multilayer stacks 114S, in accordance withsome embodiments. The removal process for forming the recesses 116 aincludes an etching process, such as an anisotropic etching process(e.g., a dry etching process), in accordance with some embodiments.

FIG. 1F-1 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line I-I′ in FIG. 1F, in accordancewith some embodiments. As shown in FIGS. 1E, 1F, and 1F-1, portions ofthe sacrificial layers 114 a are removed from sidewalls S1 of thesacrificial layers 114 a to form recesses R1 in the multilayer stacks114S, in accordance with some embodiments. Each recess R1 is surroundedby the corresponding sacrificial layer 114 a and the correspondingchannel layers 114 b, in accordance with some embodiments. The removalprocess includes an etching process, such as an isotropic etchingprocess (e.g., a dry etching process or a wet etching process), inaccordance with some embodiments.

As shown in FIG. 1F, inner spacers 170 and bottom spacers 180 arerespectively formed in the recesses R1 and 116 a, in accordance withsome embodiments. Each bottom spacer 180 includes layers 182 and 184, inaccordance with some embodiments. The layer 184 is over the layer 182,in accordance with some embodiments. The layer 182 and the inner spacers170 are formed from the same spacer material layer and therefore aremade of the same material, in accordance with some embodiments.

The layers 182 and 184 are made of different materials, in accordancewith some embodiments. In some embodiments, the layer 182 or 184 or theinner spacers 170 are made of an oxide-containing insulating material,such as silicon oxide. In some other embodiments, the layer 182 or 184or the inner spacers 170 are made of a nitride-containing insulatingmaterial, such as silicon nitride (SiN), silicon oxynitride (SiON),silicon oxycarbonitride (SiOCN), or silicon carbonitride (SiCN).

The formation of the inner spacers 170 and the bottom spacers 180includes: depositing a spacer material layer 202 (as shown in FIG. 2)over the multilayer stacks 114S, the bottom portions 115, the gatestacks 150, the mask layers M1 and M2, and the spacers 165, 166, 167,and 168, wherein the spacer material layer 202 fills the recesses R1,and the spacer material layer 202 has trenches 212 over and in therecesses 116 a; filling the layer 184 into the trenches 212 (as shown inFIG. 2); and performing an etching back process to remove portions ofthe spacer material layer 202 and the layer 184 so as to form the innerspacers 170 and the bottom spacers 180 (as shown in FIG. 1F-1), inaccordance with some embodiments. As shown in FIGS. 1F-1 and 2, theinner spacers 170 and the layer 182 of each bottom spacer 180 are formedfrom the spacer material layer 202, in accordance with some embodiments.The etching back process includes an isotropic etching process, inaccordance with some embodiments.

As shown in FIG. 1F-1, sidewalls S2, S3, S4, and S5 of the channellayers 114 b are respectively and substantially coplanar with sidewalls165 a, 166 a, 167 a, and 168 a of the spacers 165, 166, 167, and 168, inaccordance with some embodiments.

FIG. 1G-1 is a top view of the semiconductor device structure of FIG.1G, in accordance with some embodiments. FIG. 1G-2 is a cross-sectionalview illustrating the semiconductor device structure along a sectionalline I-I′ in FIG. 1G-1, in accordance with some embodiments.

As shown in FIGS. 1G, 1G-1, and 1G-2, a mask layer 190 is formed overportions of sidewalls of the fin structures 116, in accordance with someembodiments. Specifically, the mask layer 190 covers portions ofsidewalls of the multilayer stacks 114S of the fin structures 116, inaccordance with some embodiments.

As shown in FIGS. 1E-1, 1F, and 1G-1, the multilayer stacks 114Sincludes multilayer stacks 114S1, 114S2, 114S3, 114S4, 114S5, and 114S6,in accordance with some embodiments. The multilayer stack 114S1 hasopposite sidewalls SA1 and SA2, in accordance with some embodiments. Themultilayer stack 114S2 has opposite sidewalls SA3 and SA4, in accordancewith some embodiments.

The multilayer stack 114S3 has opposite sidewalls SA5 and SA6, inaccordance with some embodiments. The multilayer stack 114S4 hasopposite sidewalls SA7 and SA8, in accordance with some embodiments. Themultilayer stack 114S5 has opposite sidewalls SA9 and SA10, inaccordance with some embodiments. The multilayer stack 114S6 hasopposite sidewalls SA11 and SA12, in accordance with some embodiments.

As shown in FIGS. 1G, 1G-1, and 1G-2, the mask layer 190 covers thesidewall SA2 of the multilayer stack 114S1, the sidewall SA3 of themultilayer stack 114S2, the sidewalls SA5 and SA6 of the multilayerstack 114S3, and the sidewalls SA7 and SA8 of the multilayer stack114S4, in accordance with some embodiments. The mask layer 190 is usedto prevent stressors, which are formed in subsequent processes, frombeing formed over the sidewalls SA2, SA3, SA5, SA6, SA7 and SA8, inaccordance with some embodiments.

As shown in FIGS. 1G, 1G-1, and 1G-2, the mask layer 190 continuouslycovers the bottom spacer 180 adjacent to the sidewall SA5, the sidewallSA5 of the multilayer stack 114S3, the sidewall 165 a of the spacer 165,the top surface A1 of the mask layer M2, the sidewall 166 a of thespacer 166, the sidewall SA6 of the multilayer stack 114S3, the sidewallSA2 of the multilayer stack 114S1, the bottom spacer 180 between themultilayer stacks 114S3 and 114S4, the bottom spacer 180 between themultilayer stacks 114S1 and 114S2, the sidewall SA7 of the multilayerstack 114S4, the sidewall SA3 of the multilayer stack 114S2, thesidewall 167 a of the spacer 167, the sidewall 168 a of the spacer 168,the sidewall SA8 of the multilayer stack 114S4, and the bottom spacer180 adjacent to the sidewall SA8, in accordance with some embodiments.

The mask layer 190 is made of a nitride-containing material, such assilicon nitride, an oxide containing material, such as silicon oxide, ametal oxide material, or another suitable material, which is differentfrom the materials of the spacers 165, 166, 167, and 168, the bottomspacers 180, the mask layer M2, and the multilayer stacks 114S, inaccordance with some embodiments.

The mask layer 190 is formed using a deposition process, aphotolithography process, and an etching process, in accordance withsome embodiments. The deposition process includes a chemical vapordeposition process or a physical vapor deposition process, in accordancewith some embodiments.

FIG. 1G-3 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line II-II′ in FIG. 1G-1, inaccordance with some embodiments. As shown in FIGS. 1G, 1G-1, and 1G-3,stressors 210 are formed over the sidewall SA1 of the multilayer stack114S1, the sidewall SA4 of the multilayer stack 114S2, the sidewalls SA9and SA10 of the multilayer stack 114S5, and the sidewalls SA11 and SA12of the multilayer stack 114S6, in accordance with some embodiments. Asshown in FIGS. 1G and 1G-1, the stressor 210 over the sidewall SA1 is indirect contact with the channel layers 114 b of the multilayer stack114S1 and the inner spacers 170 in the multilayer stack 114S1, inaccordance with some embodiments.

As shown in FIGS. 1G and 1G-1, the stressor 210 over the sidewall SA4 isin direct contact with the channel layers 114 b of the multilayer stack114S2 and the inner spacers 170 in the multilayer stack 114S2, inaccordance with some embodiments. As shown in FIGS. 1G-1 and 1G-3, thestressor 210 over the sidewall SA9 is in direct contact with the channellayers 114 b of the multilayer stack 114S5 and the inner spacers 170 inthe multilayer stack 114S5, in accordance with some embodiments.

As shown in FIGS. 1G-1 and 1G-3, the stressor 210 over the sidewallsSA10 and SA11 is in direct contact with the channel layers 114 b of themultilayer stacks 114S5 and 114S6 and the inner spacers 170 in themultilayer stacks 114S5 and 114S6, in accordance with some embodiments.As shown in FIGS. 1G-1 and 1G-3, the stressor 210 over the sidewall SA12is in direct contact with the channel layers 114 b of the multilayerstack 114S6 and the inner spacers 170 in the multilayer stack 114S6, inaccordance with some embodiments.

As shown in FIGS. 1G and 1G-1, the stressors 210 are positioned over thecorresponding bottom spacers 180, in accordance with some embodiments.The bottom spacers 180 electrically insulate the stressors 210 thereoverfrom the bottom portions 115 of the fin structures 116 and the base 113,in accordance with some embodiments. As shown in FIG. 1G, the multilayerstack 114S1 and a lower portion of the gate stack 150 are between thestressor 210 and the mask layer 190, in accordance with someembodiments.

In some embodiments, the stressors 210 are made of a semiconductormaterial (e.g., silicon germanium) with P-type dopants, such as theGroup IIIA element, in accordance with some embodiments. The Group IIIAelement includes boron or another suitable material.

In some other embodiments, the stressors 210 are made of a semiconductormaterial (e.g., silicon) with N-type dopants, such as the Group VAelement, in accordance with some embodiments. The Group VA elementincludes phosphor (P), antimony (Sb), or another suitable Group VAmaterial. The stressors 210 are formed using an epitaxial process, inaccordance with some embodiments.

FIG. 1H-1 is a top view of the semiconductor device structure of FIG.1H, in accordance with some embodiments. FIG. 1H-2 is a cross-sectionalview illustrating the semiconductor device structure along a sectionalline I-I′ in FIG. 1H-1, in accordance with some embodiments. FIG. 1H-3is a cross-sectional view illustrating the semiconductor devicestructure along a sectional line II-II′ in FIG. 1H-1, in accordance withsome embodiments.

As shown in FIGS. 1H and 1H-1, the mask layer 190 is removed, inaccordance with some embodiments. As shown in FIGS. 1H, 1H-1 and 1H-3, amask layer 220 is formed over the stressors 210, the sidewall SA2 of themultilayer stack 114S1, and the sidewall SA3 of the multilayer stack114S2, in accordance with some embodiments. The mask layer 220 coversopposite sidewalls 150 a and 150 b and a top surface 150 c of each gatestack 150, in accordance with some embodiments.

As shown in FIGS. 1H, 1H-1 and 1H-2, stressors 230 are formed over thesidewalls SA5, SA6, SA7, and SA8, in accordance with some embodiments.In some embodiments, the stressors 230 are made of a semiconductormaterial (e.g., silicon) with N-type dopants, such as the Group VAelement, in accordance with some embodiments. The Group VA elementincludes phosphor (P), antimony (Sb), or another suitable Group VAmaterial.

In some other embodiments, the stressors 230 are made of a semiconductormaterial (e.g., silicon germanium) with P-type dopants, such as theGroup IIIA element, in accordance with some embodiments. The Group IIIAelement includes boron or another suitable material.

The stressors 210 and 230 are made of different materials, in accordancewith some embodiments. For example, the stressors 210 are made ofsilicon germanium with P-type dopants, and the stressors 230 are made ofsilicon with N-type dopants. In some embodiments, the stressors 210 aremade of silicon with N-type dopants, and the stressors 230 are made ofsilicon germanium with P-type dopants. The stressors 230 are formedusing an epitaxial process, in accordance with some embodiments.

As shown in FIG. 1I, the mask layer 220 is removed, in accordance withsome embodiments. As shown in FIG. 1I, an etch stop layer 240 is formedover the stressors 210 and 230, the dielectric fins 140, the sidewallSA2 of the multilayer stack 114S1, the sidewall SA3 of the multilayerstack 114S2, and the sidewalls 165 a, 166 a, 167 a, and 168 a of thespacers 165, 166, 167, and 168, in accordance with some embodiments.

The etch stop layer 240 continuously covers the sidewall SA2 of themultilayer stack 114S1, the bottom spacer 180 between the sidewalls SA2and SA3, and the sidewall SA3 of the multilayer stack 114S2, inaccordance with some embodiments. The etch stop layer 240 is made of anitride-containing material, such as silicon nitride (SiN), siliconoxynitride (SiON), or silicon carbonitride (SiCN), in accordance withsome embodiments.

Thereafter, as shown in FIG. 1I, a dielectric layer 250 is formed overthe etch stop layer 240, in accordance with some embodiments. The etchstop layer 240 is between the dielectric layer 250 and the multilayerstacks 114S1 and 114S2 to separate the dielectric layer 250 from themultilayer stacks 114S1 and 114S2, in accordance with some embodiments.The channel layers 114 b of the multilayer stack 114S1 are electricallyinsulated from the channel layers 114 b of the multilayer stack 11452 bythe dielectric layer 250, in accordance with some embodiments.

The dielectric layer 250 is made of an oxide-containing insulatingmaterial, such as silicon oxide, or a nitride-containing insulatingmaterial, such as silicon nitride, silicon oxynitride, siliconoxycarbonitride, or silicon carbonitride, in accordance with someembodiments.

FIG. 1J-1 is a perspective view of a portion of the semiconductor devicestructure of FIG. 1J, in accordance with some embodiments. For the sakeof clear illustration, FIG. 1J-1 omits portions of the dielectric layer250, the etch stop layer 240, the stressors 210 and 230, and the spacer168, in accordance with some embodiments.

As shown in FIGS. 1J and 1J-1, the gate electrodes 154 are removed toform trenches TR1 and TR2, in accordance with some embodiments. Thetrench TR1 is between the spacers 165 and 166, in accordance with someembodiments. The trench TR2 is between the spacers 167 and 168, inaccordance with some embodiments. The removal process includes anetching process, such as a wet etching process or a dry etching process,in accordance with some embodiments.

FIG. 1K-1 is a perspective view of a portion of the semiconductor devicestructure of FIG. 1K, in accordance with some embodiments. For the sakeof clear illustration, FIG. 1K-1 omits portions of the dielectric layer250, the etch stop layer 240, the stressors 210 and 230, and the spacer168, in accordance with some embodiments.

As shown in FIGS. 1J, 1K and 1K-1, the gate dielectric layers 152 areremoved through the trenches TR1 and TR2, in accordance with someembodiments. The removal process includes an etching process, such as awet etching process or a dry etching process, in accordance with someembodiments.

Thereafter, as shown in FIGS. 1K and 1K-1, the sacrificial layers 114 aare removed through the trenches TR1 and TR2, in accordance with someembodiments. The removal process includes an etching process, such as awet etching process or a dry etching process, in accordance with someembodiments.

FIG. 1L-1 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line I-I′ in FIG. 1L, in accordancewith some embodiments. As shown in FIGS. 1L and 1L-1, gate stacks 260are formed in the trenches TR1 and TR2, in accordance with someembodiments. Each gate stack 260 includes a gate dielectric layer 262, awork function layer 264, and a gate electrode layer 266, in accordancewith some embodiments.

The gate dielectric layer 262, the work function layer 264, and the gateelectrode layer 266 are sequentially stacked over the channel layers 114b, in accordance with some embodiments. The gate stack 260 wraps aroundthe channel layers 114 b, in accordance with some embodiments. In someembodiments, a portion of the gate stack 260 is between the channellayer 114 b and the bottom portion 115 (or the base 113).

Thereafter, as shown in FIGS. 1L and 1L-1, a through hole 268 is formedin each gate stack 260 to divide each gate stack 260 into gate stacks260 a and 260 b, in accordance with some embodiments. The through hole268 is formed using an etching process, such as a dry etching process,in accordance with some embodiments.

Afterwards, as shown in FIGS. 1L and 1L-1, dielectric structures 270 areformed in the through holes 268, in accordance with some embodiments.The dielectric structures 270 are made of an oxide-containing insulatingmaterial (e.g., silicon oxide), a nitride-containing insulating material(e.g., silicon nitride, silicon oxynitride, silicon oxycarbonitride, orsilicon carbonitride), or silicon carbide, in accordance with someembodiments.

FIG. 1M-1 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line I-I′ in FIG. 1M, in accordancewith some embodiments. FIG. 1M-2 is a cross-sectional view illustratingthe semiconductor device structure along a sectional line II-II′ in FIG.1M, in accordance with some embodiments.

As shown in FIGS. 1M, 1M-1, and 1M-2, portions of the dielectric layer250 are removed to form trenches 252 and 254 in the dielectric layer250, in accordance with some embodiments. Each trench 252 exposes thestressors 210 and 230, in accordance with some embodiments. As shown inFIG. 1M-1, the trench 254 exposes the stressor 230 and the dielectriclayer 250 between the multilayer stacks 114S1 and 114S2, in accordancewith some embodiments.

As shown in FIGS. 1M, 1M-1, and 1M-2, contact structures 282 and 284 arerespectively formed in the trenches 252 and 254, in accordance with someembodiments. In this step, a semiconductor device structure 200 issubstantially formed, in accordance with some embodiments. Thesemiconductor device structure 200 is used in, for example, a staticrandom access memory (SRAM) device. The contact structure 282 is indirect contact with and is electrically connected to the stressors 210and 230 thereunder, in accordance with some embodiments.

The contact structure 284 is between the gate stacks 260 a, between thedielectric structures 270, between the gate stacks 260 b, between themultilayer stacks 114S1 and 114S2, and between the multilayer stacks114S3 and 114S4 (as shown in FIG. 1H-1), in accordance with someembodiments. As shown in FIG. 1M, the contact structure 284 is in directcontact with and is electrically connected to the stressor 230thereunder, in accordance with some embodiments. The contact structure284 is in direct contact with the dielectric fins 140, the etch stoplayer 240, and the dielectric layer 250 thereunder, in accordance withsome embodiments.

In some embodiments, a bottom surface 284 a of the contact structure 284is lower than a bottom surface 282 a of the contact structures 282. Thecontact structure 284 is between the channel layers 114 b of themultilayer stack 114S1 or 114S2, in accordance with some embodiments.

The contact structures 282 and 284 are made of tungsten (W), cobalt(Co), aluminum (Al), ruthenium (Ru), copper (Cu) or another suitableconductive material, in accordance with some embodiments. The formationof the contact structures 282 and 284 includes depositing a conductivematerial layer (not shown) over the dielectric layer 250 and in thetrenches 252 and 254; and performing a chemical mechanical polishing(CMP) process over the conductive material layer to remove theconductive material layer outside of the trenches 252 and 254.

The embodiments prevent the stressors 210 and 230 from being formed overthe sidewalls S3 and S4 by using the mask layers 190 and 220, inaccordance with some embodiments. The dielectric layer 250 formed overthe stressors 210 and 230 is also filled into the trench between thesidewalls S3 and S4, and therefore the dielectric layer 250 is able tobe self-aligned with the multilayer stacks 114S1 and 114S2 and the gatestacks 260 a thereover, in accordance with some embodiments. Therefore,there is no need to perform any additional process to form a trench anda dielectric layer in the trench in the fin structures 116 before theformation of the gate stacks 150 of FIG. 1C, in accordance with someembodiments. As a result, there is no need to maintain alignmentaccuracy between the dielectric layer 250 and the gate stacks 260 a (orthe multilayer stacks 114S1 and 114S2). Therefore, the manufacturingprocess is simplified, production cost is reduced, the manufacturingtime is shortened, productivity is increased, and the yield of thesemiconductor device structure 200 is improved.

As shown in FIG. 1M-2, a thickness T1 of the channel layer 114 b rangesfrom about 2 nm to about 10 nm, in accordance with some embodiments. Insome embodiments, a width W1 of the channel layer 114 b ranges fromabout 5 nm to about 70 nm, in accordance with some embodiments. In someembodiments, a thickness T2 of the etch stop layer 240 ranges from about2 nm to about 10 nm. In some embodiments, a thickness T3 of the spacer165, 166, 167, or 168 ranges from about 2 nm to about 10 nm.

In some embodiments, a width W2 of the contact structure 282 ranges fromabout 5 nm to about 30 nm, in accordance with some embodiments. In someembodiments, a length L of the contact structure 282 ranges from about 3nm to about 40 nm, in accordance with some embodiments.

In some embodiments, a width W3 of the gate stack 260 a ranges fromabout 4 nm to about 25 nm, in accordance with some embodiments. In someembodiments, a width W4 of the inner spacer 170 ranges from about 2 nmto about 20 nm. In some embodiments, the dielectric layer 250 betweenthe multilayer stacks 114S1 and 114S2 has a recess R2 with a depth Dwith respect to a top surface 114 b 1 or 114 b 2 of the multilayer stack114S1 or 114S2. The depth D ranges from about 1 nm to about 20 nm, inaccordance with some embodiments. In some other embodiments, the depth Dis about 0 nm, and the recess R2 is almost invisible.

As shown in FIG. 1M-2, the sidewalls S2, S3, S4, and S5 of the channellayers 114 b are respectively and substantially coplanar with sidewalls165 a, 166 a, 167 a, and 168 a of the spacers 165, 166, 167, and 168, inaccordance with some embodiments. As shown in FIG. 1M-2, the sidewallsS2, S3, S4, and S5 of the channel layers 114 b are respectively andsubstantially coplanar with the sidewalls 172, 174, 176, and 178 of theinner spacers 170, in accordance with some embodiments. In some otherembodiments, as shown in FIGS. 3 and 4, the sidewalls S2, S3, S4, and S5of the channel layers 114 b are misaligned with the sidewalls 172, 174,176, and 178 of the inner spacers 170, in accordance with someembodiments.

As shown in FIG. 3, the sidewall 172 is recessed from the sidewalls S2,in accordance with some embodiments. The sidewall 174 is recessed fromthe sidewalls S3, in accordance with some embodiments. The sidewall 176is recessed from the sidewalls S4, in accordance with some embodiments.The sidewall 178 is recessed from the sidewalls S5, in accordance withsome embodiments. The channel layers 114 b laterally extend out of thesidewalls 172, 174, 176, and 178 of the inner spacers 170, whichimproves the formation of the stressors 210 over the channel layers 114b, in accordance with some embodiments.

As shown in FIG. 3, a distance D1 is between the sidewalls 172 and S2,in accordance with some embodiments. A distance D2 is between thesidewalls 174 and S3, in accordance with some embodiments. A distance D3is between the sidewalls 176 and S4, in accordance with someembodiments. A distance D4 is between the sidewalls 178 and S5, inaccordance with some embodiments.

In some embodiments, the distance D1 is different from the distance D2.In some other embodiments, the distance D1 is substantially equal to thedistance D2. The term “substantially equal to” in the application means“within 10%”, in accordance with some embodiments. For example, the term“substantially equal to” means the difference between the distances D1and D2 is within 10% of the average of the distances D1 and D2, inaccordance with some embodiments. The difference may be due tomanufacturing processes.

In some embodiments, the distance D3 is different from the distance D4.In some other embodiments, the distance D3 is substantially equal to thedistance D4. The term “substantially equal to” in the application means“within 10%”, in accordance with some embodiments. For example, the term“substantially equal to” means the difference between the distances D3and D4 is within 10% of the average of the distances D3 and D4, inaccordance with some embodiments. The difference may be due tomanufacturing processes. The distance D1, D2, D3, or D4 ranges fromabout 1 nm to about 3 nm, in accordance with some embodiments.

As shown in FIG. 4, the sidewall S2 is recessed from the sidewalls 172,in accordance with some embodiments. The sidewall S3 is recessed fromthe sidewalls 174, in accordance with some embodiments. The sidewall S4is recessed from the sidewalls 176, in accordance with some embodiments.The sidewall S5 is recessed from the sidewalls 178, in accordance withsome embodiments. The channel layers 114 b are shortened with respect tothe channel layers 114 b of FIG. 1M-2, and therefore the channel lengthis shorten, in accordance with some embodiments.

The forming method of the channel layers 114 b of FIG. 4 is similar tothat of the channel layers 114 b of FIG. 1M-2, except that the formationof the channel layers 114 b of FIG. 4 further includes performing anetching back process over sidewalls of the channel layers 114 b afterthe formation of the inner spacers 170 of FIG. 1F and before theformation of the stressors 210, in accordance with some embodiments.

As shown in FIG. 4, a distance D5 is between the sidewalls 172 and S2,in accordance with some embodiments. A distance D6 is between thesidewalls 174 and S3, in accordance with some embodiments. A distance D7is between the sidewalls 176 and S4, in accordance with someembodiments. A distance D8 is between the sidewalls 178 and S5, inaccordance with some embodiments.

In some embodiments, the distance D5 is different from the distance D6.In some other embodiments, the distance D5 is substantially equal to thedistance D6. The term “substantially equal to” in the application means“within 10%”, in accordance with some embodiments. For example, the term“substantially equal to” means the difference between the distances D5and D6 is within 10% of the average of the distances D5 and D6, inaccordance with some embodiments. The difference may be due tomanufacturing processes.

In some embodiments, the distance D7 is different from the distance D8.In some other embodiments, the distance D7 is substantially equal to thedistance D8. The term “substantially equal to” in the application means“within 10%”, in accordance with some embodiments. For example, the term“substantially equal to” means the difference between the distances D7and D8 is within 10% of the average of the distances D7 and D8, inaccordance with some embodiments. The difference may be due tomanufacturing processes. The distance D5, D6, D7, or D8 ranges fromabout 1 nm to about 3 nm, in accordance with some embodiments.

Although FIG. 1M-2 shows that one side of the multilayer stack (e.g.,the multilayer stack 114S1) is connected to the stressor 210, and theother side of the multilayer stack is covered by the dielectric layer250 to be electrically insulated from the adjacent multilayer stack(e.g., the multilayer stack 114S2), the embodiments are not limitedthereto. For example, as shown in FIG. 5, two opposite sides of themultilayer stack 114S7 are both covered by the dielectric layer 250 tobe electrically insulated from two adjacent multilayer stacks 114S1 and114S2.

FIG. 5 is a cross-sectional view of a semiconductor device structure500, in accordance with some embodiments. As shown in FIG. 5, thesemiconductor device structure 500 is similar to the semiconductordevice structure 200 of FIG. 1M-2, except that the semiconductor devicestructure 500 further includes a gate stack 260 a′, spacers 169, themultilayer stack 114S7, and a contact structure 284′, in accordance withsome embodiments.

The gate stack 260 a′ is over and wraps around the multilayer stack114S7, in accordance with some embodiments. The spacers 169 are onopposite sides of the gate stack 260 a′, in accordance with someembodiments. The spacers 169 are over the multilayer stack 114S7, inaccordance with some embodiments. The gate stack 260 a′ is between thecontact structures 284 and 284′, in accordance with some embodiments.The dielectric layer 250 is on opposite sides of the multilayer stack114S7 to electrically insulate the multilayer stack 114S7 from themultilayer stacks 114S1 and 114S2, in accordance with some embodiments.

The forming method of the semiconductor device structure 500 is similarto the semiconductor device structure 200 of FIG. 1M-2, except that themask layer 190 (as shown in FIG. 6A) further covers the oppositesidewalls SA13 and SA14 of the multilayer stack 114S7 while forming thestressors 210 to prevent the stressors 210 from being formed over thesidewalls SA13 and SA14, and the mask layer 220 (as shown in FIG. 6B)further covers the sidewalls SA13 and SA14 while forming the stressors230 (as shown in FIG. 1H) to prevent the stressors 230 from being formedover the sidewalls SA13 and SA14, in accordance with some embodiments.

In FIGS. 6A and 6B, a gate stack 150′ over the multilayer stack 114S7wraps around the multilayer stack 114S7, in accordance with someembodiments. The forming methods, the materials, and the structures ofthe gate stack 260 a′, the spacers 169, the multilayer stack 114S7, andthe contact structure 284′ are similar to or substantially the same asthe gate stack 260 a, the spacers 165 and 166, the multilayer stack114S1, and the contact structure 284 of FIG. 1M-2. The forming methods,the materials, and the structures of the gate stack 150′ are similar toor substantially the same as the gate stack 150 of FIG. 1H, inaccordance with some embodiments.

FIGS. 7A-7E are cross-sectional views of various stages of a process forforming a semiconductor device structure, in accordance with someembodiments. After the step of FIG. 1D, as shown in FIG. 7A, portions ofthe spacer layer 160 are removed, in accordance with some embodiments.After the removal process, the spacer layer 160 remains over oppositesidewalls of the gate stacks 150, opposite sidewalls of the mask layersM1 and M2, and the top surfaces 132 of the dielectric layer 130, inaccordance with some embodiments.

The spacer layer 160 remaining over the opposite sidewalls of the gatestacks 150 and the opposite sidewalls of the mask layers M1 and M2 formsspacers 165, 166, 167, and 168, in accordance with some embodiments. Thespacer layer 160 remaining over the top surfaces 132 of the dielectriclayer 130 forms spacers 169, in accordance with some embodiments.

Afterwards, as shown in FIG. 7A, a mask layer 710 is formed over themiddle one of the fin structures 116, in accordance with someembodiments. The mask layer 710 covers the entire fin structure 116thereunder, the spacers 169 adjacent to the fin structure 116 covered bythe mask layer 710, portions of the spacer layer 160, and portions ofthe mask layer M2, in accordance with some embodiments.

Thereafter, as shown in FIG. 7A, upper portions of the fin structures116, which are not covered by the mask layer 710, the gate stacks 150and the spacer layer 160, are removed, in accordance with someembodiments. The removal process forms recesses 116 a in the finstructures 116, in accordance with some embodiments. The multilayerstructure 114 is divided into multilayer stacks 114S by the recesses 116a, in accordance with some embodiments. Each multilayer stack 114Sincludes four layers of the sacrificial layers 114 a and four layers ofthe channel layers 114 b, in accordance with some embodiments.

Afterwards, as shown in FIGS. 7A and 7B, portions of the sacrificiallayers 114 a, which are not covered by the mask layer 710, are removedfrom sidewalls S1 of the sacrificial layers 114 a to form recesses R1 inthe multilayer stacks 114S, in accordance with some embodiments. Eachrecess R1 is surrounded by the corresponding sacrificial layer 114 a andthe corresponding channel layers 114 b, in accordance with someembodiments. The removal process includes an etching process, such as anisotropic etching process (e.g., a dry etching process or a wet etchingprocess), in accordance with some embodiments.

Afterwards, as shown in FIGS. 7A and 7B, inner spacers 170 and bottomspacers 180 are respectively formed in the recesses R1 and 116 a, inaccordance with some embodiments. Each bottom spacer 180 includes layers182 and 184, in accordance with some embodiments. The layer 184 is overthe layer 182, in accordance with some embodiments. The layer 182 andthe inner spacers 170 are formed from the same spacer material layer andtherefore are made of the same material, in accordance with someembodiments.

The layers 182 and 184 are made of different materials, in accordancewith some embodiments. In some embodiments, the layer 182 or 184 or theinner spacers 170 are made of an oxide-containing insulating material,such as silicon oxide. In some other embodiments, the layer 182 or 184or the inner spacers 170 are made of a nitride-containing insulatingmaterial, such as silicon nitride (SiN), silicon oxynitride (SiON),silicon oxycarbonitride (SiOCN), or silicon carbonitride (SiCN).

Thereafter, as shown in FIG. 7B, the mask layer 710 is removed, inaccordance with some embodiments. Afterwards, as shown in FIG. 7B, thestep of FIG. 1G is performed to form the mask layer 190 and thestressors 210, in accordance with some embodiments. The mask layer 190covers the middle one of the fin structures 116, the sidewall SA2 of themultilayer stack 114S1, and the sidewall SA3 of the multilayer stack11452, in accordance with some embodiments.

The formation positions, the materials, the structures, and the formingmethods of the mask layer 190 and the stressors 210 of FIG. 7B aresimilar to or substantially the same as the mask layer 190 and thestressors 210 of FIG. 1G, in accordance with some embodiments.

As shown in FIG. 7C, the mask layer 190 is removed, in accordance withsome embodiments. As shown in FIG. 7C, a mask layer 220 is formed overthe stressors 210, the sidewall SA2 of the multilayer stack 114S1, andthe sidewall SA3 of the multilayer stack 114S2, in accordance with someembodiments. The mask layer 220 covers opposite sidewalls 150 a and 150b and a top surface 150 c of each gate stack 150, in accordance withsome embodiments.

FIG. 7C-1 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line I-I′ in FIG. 7C, in accordancewith some embodiments. As shown in FIGS. 7C and 7C-1, upper portions ofthe fin structures 116, which are not covered by the mask layer 220, thegate stacks 150 and the spacer layer 160, are removed, in accordancewith some embodiments.

The removal process forms recesses 116 a in the fin structures 116, inaccordance with some embodiments. The multilayer structure 114 isdivided into multilayer stacks 114S by the recesses 116 a, in accordancewith some embodiments. Each multilayer stack 114S includes four layersof the sacrificial layers 114 a and four layers of the channel layers114 b, in accordance with some embodiments.

Afterwards, as shown in FIGS. 7C and 7C-1, portions of the sacrificiallayers 114 a, which are not covered by the mask layer 220, are removedfrom sidewalls of the sacrificial layers 114 a to form recesses R1 inthe multilayer stacks 114S, in accordance with some embodiments. Eachrecess R1 is surrounded by the corresponding sacrificial layer 114 a andthe corresponding channel layers 114 b, in accordance with someembodiments. The removal process includes an etching process, such as anisotropic etching process (e.g., a dry etching process or a wet etchingprocess), in accordance with some embodiments.

Afterwards, as shown in FIGS. 7C and 7C-1, inner spacers 720 and bottomspacers 730 are respectively formed in the recesses R1 and 116 a, inaccordance with some embodiments. Each bottom spacer 730 includes layers732 and 734, in accordance with some embodiments. The layer 734 is overthe layer 732, in accordance with some embodiments. The layer 732 andthe inner spacers 720 are formed from the same spacer material layer andtherefore are made of the same material, in accordance with someembodiments.

The layers 732 and 734 are made of different materials, in accordancewith some embodiments. In some embodiments, the layer 732 or 734 or theinner spacers 720 are made of an oxide-containing insulating material,such as silicon oxide. In some other embodiments, the layer 732 or 734or the inner spacers 720 are made of a nitride-containing insulatingmaterial, such as silicon nitride (SiN), silicon oxynitride (SiON),silicon oxycarbonitride (SiOCN), or silicon carbonitride (SiCN).

FIG. 7D-1 is a cross-sectional view illustrating the semiconductordevice structure along a sectional line I-I′ in FIG. 7D, in accordancewith some embodiments. As shown in FIGS. 7D and 7D-1, stressors 230 areformed over the sidewalls SA5 and SA6 of the multilayer stack 11453 andthe sidewalls SA7 and SA8 of the multilayer stack 11454, in accordancewith some embodiments. In some embodiments, the stressors 230 are madeof a semiconductor material (e.g., silicon) with N-type dopants, such asthe Group VA element, in accordance with some embodiments. The Group VAelement includes phosphor (P), antimony (Sb), or another suitable GroupVA material.

In some other embodiments, the stressors 230 are made of a semiconductormaterial (e.g., silicon germanium) with P-type dopants, such as theGroup IIIA element, in accordance with some embodiments. The Group IIIAelement includes boron or another suitable material.

The stressors 210 and 230 are made of different materials, in accordancewith some embodiments. For example, the stressors 210 are made ofsilicon germanium with P-type dopants, and the stressors 230 are made ofsilicon with N-type dopants. In some embodiments, the stressors 210 aremade of silicon with N-type dopants, and the stressors 230 are made ofsilicon germanium with P-type dopants. The stressors 230 are formedusing an epitaxial process, in accordance with some embodiments.

As shown in FIG. 7E, the mask layer 220 is removed, in accordance withsome embodiments. Afterwards, as shown in FIG. 7E, the steps of FIGS.1I-1M are performed, in accordance with some embodiments. In this step,a semiconductor device structure 700 is substantially formed, inaccordance with some embodiments.

Processes and materials for forming the semiconductor structures of FIG.2 to FIG. 7E may be similar to, or the same as, those for forming thesemiconductor structure 200 described above.

In accordance with some embodiments, semiconductor device structures andmethods for forming the same are provided. The methods (for forming thesemiconductor device structure) form a stressor over one sidewall of themultilayer stack while a mask layer covers the other sidewall of themultilayer stack to prevent the stressor from being formed over theother sidewall. The methods remove the mask layer and form a dielectriclayer over the other sidewall to electrically insulate the multilayerstack from an adjacent multilayer stack. The dielectric layer isself-aligned with the multilayer stack and a gate stack over themultilayer stack. Therefore, there is no need to maintain alignmentaccuracy between the dielectric layer and the multilayer stack (or thegate stack). Therefore, production cost is reduced, and the yield of thesemiconductor device structures is improved.

In accordance with some embodiments, a semiconductor device structure isprovided. The semiconductor device structure includes a substrate havinga base and a multilayer stack over the base. The semiconductor devicestructure includes a gate stack over the substrate and wrapping aroundthe multilayer stack. The semiconductor device structure includes adielectric layer over the base and covering a first sidewall of themultilayer stack. A first upper surface of the dielectric layer is lowerthan a second upper surface of the multilayer stack. The semiconductordevice structure includes a stressor over a second sidewall of themultilayer stack. The first sidewall is opposite to the second sidewall.

In accordance with some embodiments, a semiconductor device structure isprovided. The semiconductor device structure includes a substrate havinga base, a first multilayer stack, and a second multilayer stack over thebase. The first multilayer stack and the second multilayer stack areseparated by a gap. The semiconductor device structure includes a firstgate stack and a second gate stack over the substrate. The first gatestack wraps around the first multilayer stack, and the second gate stackwraps around the second multilayer stack. The semiconductor devicestructure includes a dielectric layer in the gap and covering a firstsidewall of the first multilayer stack and a second sidewall of thesecond multilayer stack. The first sidewall and the second sidewall faceeach other. The semiconductor device structure includes a first stressorover a third sidewall of the first multilayer stack. The first sidewallis opposite to the third sidewall.

In accordance with some embodiments, a semiconductor device structure isprovided. The semiconductor device structure includes a substrate havinga base and a first multilayer stack over the base. The semiconductordevice structure includes a first gate stack over the substrate. Thefirst gate stack wraps around the first multilayer stack. Thesemiconductor device structure includes a first spacer over a firstsidewall of the first gate stack. A second sidewall of the first spaceris substantially level with a third sidewall of the first multilayerstack. The semiconductor device structure includes a dielectric layerover the base and covering the third sidewall. The semiconductor devicestructure includes a stressor over a fourth sidewall of the firstmultilayer stack. The third sidewall is opposite to the fourth sidewall.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A semiconductor device structure, comprising: asubstrate having a base and a multilayer stack over the base; a gatestack over the substrate and wrapping around the multilayer stack; adielectric layer over the base and covering a first sidewall of themultilayer stack, wherein a first upper surface of the dielectric layeris lower than a second upper surface of the multilayer stack; and astressor over a second sidewall of the multilayer stack, wherein thefirst sidewall is opposite to the second sidewall.
 2. The semiconductordevice structure as claimed in claim 1, wherein the second upper surfaceof the multilayer stack is lower than a third upper surface of thestressor.
 3. The semiconductor device structure as claimed in claim 1,wherein the first upper surface of the dielectric layer is a concavesurface.
 4. The semiconductor device structure as claimed in claim 1,further comprising: an etch stop layer covering the first sidewall ofthe multilayer stack and between the dielectric layer and the multilayerstack.
 5. The semiconductor device structure as claimed in claim 4,wherein the etch stop layer continuously covers the first sidewall ofthe multilayer stack and a third sidewall of the gate stack.
 6. Thesemiconductor device structure as claimed in claim 1, furthercomprising: a dummy contact structure over the dielectric layer.
 7. Thesemiconductor device structure as claimed in claim 6, wherein the dummycontact structure partially extends into the dielectric layer.
 8. Thesemiconductor device structure as claimed in claim 6, wherein a bottomsurface of the dummy contact structure is lower than the second uppersurface of the multilayer stack.
 9. The semiconductor device structureas claimed in claim 8, wherein the bottom surface of the dummy contactstructure is a convex surface.
 10. The semiconductor device structure asclaimed in claim 6, further comprising: an etch stop layer covering thefirst sidewall of the multilayer stack and between the dielectric layerand the multilayer stack and between the dummy contact structure and themultilayer stack.
 11. A semiconductor device structure, comprising: asubstrate having a base, a first multilayer stack, and a secondmultilayer stack over the base, wherein the first multilayer stack andthe second multilayer stack are separated by a gap; a first gate stackand a second gate stack over the substrate, wherein the first gate stackwraps around the first multilayer stack, and the second gate stack wrapsaround the second multilayer stack; a dielectric layer in the gap andcovering a first sidewall of the first multilayer stack and a secondsidewall of the second multilayer stack, wherein the first sidewall andthe second sidewall face each other; and a first stressor over a thirdsidewall of the first multilayer stack, wherein the first sidewall isopposite to the third sidewall.
 12. The semiconductor device structureas claimed in claim 11, further comprising: a second stressor over afourth sidewall of the second multilayer stack, wherein the secondsidewall is opposite to the fourth sidewall.
 13. The semiconductordevice structure as claimed in claim 11, further comprising: an etchstop layer continuously covering the first sidewall of the firstmultilayer stack and the second sidewall of the second multilayer stackand between the dielectric layer and the base.
 14. The semiconductordevice structure as claimed in claim 13, wherein the etch stop layer hasa U-like shape.
 15. The semiconductor device structure as claimed inclaim 13, further comprising: a bottom spacer between the dielectriclayer and the base of the substrate, wherein the etch stop layer isbetween the dielectric layer and the bottom spacer.
 16. A semiconductordevice structure, comprising: a substrate having a base and a firstmultilayer stack over the base; a first gate stack over the substrate,wherein the first gate stack wraps around the first multilayer stack; afirst spacer over a first sidewall of the first gate stack, wherein asecond sidewall of the first spacer is substantially level with a thirdsidewall of the first multilayer stack; a dielectric layer over the baseand covering the third sidewall; and a stressor over a fourth sidewallof the first multilayer stack, wherein the third sidewall is opposite tothe fourth sidewall.
 17. The semiconductor device structure as claimedin claim 16, wherein the stressor is in direct contact with the firstmultilayer stack.
 18. The semiconductor device structure as claimed inclaim 16, further comprising: an etch stop layer continuously coveringthe second sidewall and the third sidewall, wherein the etch stop layeris between the dielectric layer and the first multilayer stack.
 19. Thesemiconductor device structure as claimed in claim 16, wherein thesubstrate further has a second multilayer stack over the base, and thesemiconductor device structure further comprises: a second gate stackover the substrate, wherein the second gate stack wraps around thesecond multilayer stack; a second spacer over a fifth sidewall of thesecond gate stack, wherein a sixth sidewall of the second spacer islevel with a seventh sidewall of the second multilayer stack, and thedielectric layer further covers the seventh sidewall; and a secondstressor over an eighth sidewall of the second multilayer stack, whereinthe seventh sidewall is opposite to the eighth sidewall.
 20. Thesemiconductor device structure as claimed in claim 19, furthercomprising: a contact structure between the first gate stack and thesecond gate stack and between the first multilayer stack and the secondmultilayer stack, wherein the contact structure is over the dielectriclayer.